Graduate Research Assistant

• Developing a GNN-based power and EM side-channel leakage modeling framework at the pre-silicon stage to enhance the security of cryptographic designs against physical attacks.
• Designing an EM-based side-channel disassembler to reconstruct executed instructions in microcontrollers, contributing to secure embedded systems analysis.
• Developed a novel PMU-based approach for detecting CPU workloads and mitigating cache side-channel vulnerabilities to counter speculative execution attacks.
• Implemented an automated CAD toolflow to assess physical-design-aware EM side-channel vulnerability at the gate level, in support of the CYAN Research Program, enabling rapid pre-silicon security sign-off.
• Built a Python-based framework to estimate IP and SoC-level resilience against power side-channel threats at the RTL level as part of a DARPA AISS project in collaboration with Synopsys. • Designed security primitive IPs in RTL for device lifecycle management as part of the DARPA AISS project in collaboration with Synopsys.

Graduate Technical Intern

• Developed embedded applications for secure boot, TLS communication, and cryptographic services as part of the DARPA-funded AISS project.
• Implemented ASCON lightweight cryptographic applications for embedded firmware encryption and authentication within a secure boot protocol.
• Integrated ASCON authenticated encryption and hashing hardware modules into the Synopsys security engine subsystem, incorporating a masking scheme for side-channel resiliency.

Graduate Teaching Assistant

• Managed assignments, projects, and exams for "Intro to Hardware Security and Trust," helped develop tutorials on commercial EDA tools for VLSI design, synthesis, and functional and security verification.

Graduate Research Assistant

• Developed open-source API-based C++ scripts to interface with commercial DDR3 DRAM chips on a Xilinx ML605 FPGA, enabling read/write operations with configurable timing parameters.
• Analyzed device aging and retention error-induced bit-flips under stress conditions, exploring reliability and security issues while generating robust signatures.

Graduate Teaching Assistant

• Assisted 100+ graduate and undergraduate students with grading, homework, quizzes, projects, and exams on computer organization, architecture, memory hierarchy, assembly language, and MIPS ISA.

DRAM Reliability and Security Assessment

At The University of Alabama in Huntsville, my research focused on evaluating DRAM reliability and security, funded by the National Science Foundation (NSF). I developed a C++ testing framework for DDR3 DRAM on Xilinx ML605 FPGA to control and analyze retention errors under stress, yielding insights into aging vulnerabilities in memory modules. These findings were published in Applied Sciences, contributing to enhanced memory reliability.

Automatic Implementation of Secure Silicon (DARPA AISS Project)

As part of the DARPA AISS Project at the Florida Institute for Cybersecurity (FICS) Research, I developed scalable security solutions to enhance IP and SoC resilience against side-channel threats. Key contributions included a Python-based framework to assess power side-channel vulnerabilities at the RTL level and the development of security primitives for device lifecycle management, such as secure boot protocols and a silicon odometer for lifecycle tracking. This collaborative project with Synopsys has yielded published results in the Cryptology ePrint Archive, and presented in IEEE Xplore, and featured in Semiconductor Engineering.

CYAN Research Program

In the CYAN Research Program, I contributed to advancing pre-silicon side-channel security for cryptographic designs. I implemented an automated CAD toolflow to evaluate gate-level, physical-design-aware electromagnetic (EM) side-channel vulnerabilities, enabling rapid security sign-off at the pre-silicon stage. This toolflow was presented at the GOMACTech Workshop 2023. Currently, I am developing a Graph Neural Network (GNN)-based framework to model power and EM side-channel leakage, further strengthening cryptographic resilience against physical attacks by identifying potential vulnerabilities during early design stages.

PMU-Based Side-Channel Profiling of User Activity

In this ongoing project, I developed techniques using Performance Monitoring Units (PMUs) to detect CPU workload patterns, with an emphasis on cache side-channel profiling to expose speculative execution vulnerabilities. This approach sheds light on modern processor security challenges, underscoring the importance of PMU data in analyzing user activity patterns.

Secure Embedded Applications (Synopsys Inc.)

As a Graduate Technical Intern at Synopsys Inc., I worked on secure boot protocols and cryptographic applications for embedded systems, including TLS communication for data integrity. I integrated ASCON lightweight cryptography, enhancing cryptographic resilience against side-channel attacks, which further strengthened Synopsys’s security IP portfolio.

EM-Based Side-Channel Disassembler

Currently, in collaboration with Drs. Tehranipoor and Farahmandi, I am developing an EM-based disassembler to recover executed instructions from electromagnetic (EM) emissions. This disassembler supports firmware verification by analyzing EM signals for defense and critical infrastructure applications, helping to verify software integrity and detect anomalies in secure systems.